1. Field of the Invention
The invention relates generally to the testing of electronic circuits, and more particularly to systems and methods for performing logic built-in self-tests (LBISTs) using circuitry that enables the isolation of scan chains in selected portions of the functional logic of a device under test.
2. Related Art
Digital devices are becoming increasingly complex. As the complexity of these devices increases, there are more and more chances for defects that may impair or impede proper operation of the devices. The testing of these devices is therefore becoming increasingly important.
Testing of a device may be important at various stages, including in the design of the device, in the manufacturing of the device, and in the operation of the device. Testing at the design stage ensures that the design is conceptually sound. Testing during the manufacturing stage may be performed to ensure that the timing, proper operation and performance of the device are as expected. Finally, after the device is manufactured, it may be necessary to test the device to determine whether it contains any defects that prevent it from operating properly during normal usage.
Ideally, it would be possible and/or practical to test the device for every possible defect. Because of the complexity of most devices, however, it would be prohibitively expensive to take the deterministic approach of testing every possible combination of inputs to each logic gate and states of the device. A more practical approach applies pseudorandom input test patterns to the inputs of the different logic gates. The outputs of the logic gates are then compared to the outputs generated by a “good” device (one that is known to operate properly) in response to the same pseudorandom input test patterns. The more input patterns that are tested, the higher the probability that the logic circuit being tested operates properly (assuming there are no differences between the results generated by the two devices.)
This non-deterministic approach can be implemented using logic built-in self-test (LBIST) techniques. For example, one LBIST technique (which uses what is referred to as a STUMPS architecture) involves incorporating latches between portions of the logic being tested (the target logic,) loading these latches with pseudorandom bit patterns and then capturing the bit patterns that result from the propagation of the pseudorandom data through the target logic. Conventionally, the captured bit patterns are scanned out of the scan chains into a multiple-input signature register (MISR,) in which the bit patterns are combined with an existing signature value to produce a new signature value. This signature value can be examined (e.g., compared with the signature generated in a device that is known to operate properly) to determine whether or not the device under test functioned properly during the test.
While this testing approach can be very effective, it does have some drawbacks. In some devices, such as multiprocessor integrated circuits, the device may be considered to be “good,” even if some portions of the device include defects. For instance, in a multiprocessor having N processors, the multiprocessor may still be functional if one or more of the processors is defective. Using conventional LBIST testing techniques, however, there is only a single MISR value that indicates whether the device under test produced any errors or not. Any errors that are produced during testing are combined with other data, and possibly other errors, in the MISR, so it cannot be determined whether the errors arose in a single functional block (e.g. processor) or multiple blocks, or which if the functional blocks caused the error(s).
It would therefore be desirable to provide systems and methods for implementing LBIST testing that enable the isolation of selected portions of the target logic so that errors in the isolated portions do not corrupt the MISR signature during subsequent testing.